The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 1995
Filed:
Nov. 20, 1992
Salomon Vulih, Neshanic Street, NJ (US);
John A Olmstead, Cape May Court House, NJ (US);
Harold A Wittlinger, Pennigton, NJ (US);
Harris Corporation, Melbourne, FL (US);
Abstract
An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets. The gain of the amplifier system is controlled by low pass filters connected to the output node of the input stage and to the output of the second stage. In certain embodiments a biasing clock is coupled via resistors to the inputs of the differential amplifiers to generate a dc bias level at their inputs which is a function of the duty cycle of the clock, the resistor connected at the input and coupling capacitor connected to the input.