Differential-to-single-ended converter

Abstract

First and second transistors respectively receive differential input signals each having first and second logic levels and respectively produce resultant currents dependent upon the levels of the input signals. The transistors may be CMOS transistors of the n-type with substantially identical characteristics. The input signals may be introduced to the gates of these transistors and the resultant currents may be produced at the drains of these transistors. Third and fourth transistors may receive the resultant currents. The third and fourth transistors may be CMOS transistors of the n-type with substantially identical characteristics. The resultant voltage at the first transistor may be introduced in a modified form to the third and fourth transistors to regulate the resultant voltage introduced to the third transistor and to expedite the response of the fourth transistor. The modification may be an inversion of the resultant voltage at the first transistor, the inversion being produced by an amplifier-inverter in a servo loop with the third transistor. The currents on the drains of the first and second transistors may be respectively introduced to the sources of the third and fourth transistors. The modified (or inverted) voltage from the drain of the first transistor may be introduced to the gates of the third and fourth transistors. An output voltage may be provided at the source of the fourth transistor. The output voltage may be inverted as by an amplifier-inverter having characteristics substantially identical to those of the amplifier-inverter in the servo loop.