The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 1995
Filed:
Aug. 26, 1993
Yoshihisa Koyama, Yokosuka, JP;
Taku Katayama, Yokohama, JP;
Katsuhiko Morita, Yokosuka, JP;
Masashi Yoshimura, Yokohama, JP;
Toshiki Yoshida, Miura, JP;
Manabu Endo, Yokohama, JP;
Victor Company of Japan, Ltd., Yokohama, JP;
Abstract
An LED (light emitting diode) array of the present invention has a plurality of light emitting diodes aligned in row on a substrate crystal. Each of the light emitting diodes has a double hetero-structure formed by causing a light emitting layer to be interposed between p-type and n-type semi-conductive layers and is isolated with isolating mesa grooves. A reflecting layer is provided between the substrate crystal and one of the p-type and n-type semi-conductive layers. The reflecting layer comprises a plurality of semi-conductive layers having at least different refractive indexes of 2 or more than 2-kinds, each of the semi-conductive layers made of semiconductor having the same polarity as that of the substrate crystal and having a wider forbidden band width than that of the light emitting layer. Further, the isolating mesa grooves are provided by a wet etching using an etching liquid of H.sub.3 PO.sub.4 .multidot.H.sub.2 O.sub.2 having volume ratio of H.sub.3 PO.sub.4 : H.sub.2 O.sub.2 =1.about.5:1, thus, the LED array having a high integration and a high light emitting output can be successfully produced.