The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 1995
Filed:
Oct. 22, 1991
George J Barlow, Tewksbury, MA (US);
James W Keeley, Nashua, NH (US);
Bull HN Information Systems Inc., Billerica, MA (US);
Abstract
A multiprocessor computer system having a first processor having a first interrupt mechanism for generating interrupt requests, a second processor having a second interrupt mechanism, and a system bus for communicating interrupt requests from the first processor to the second processor. The second interrupt mechanism is responsive to an interrupt request by generating an acknowledge response on the system bus when the second processor accepts the interrupt request and generating a not acknowledge response on the system bus when the second processor contains a previous and pending interrupt request of higher level and refuses the interrupt request. The second interrupt mechanism is responsive to the completion of servicing of an interrupt request by the second processor by placing on the system bus an interrupt completed command, which includes an address identifying the second processor and a code indicating that the second processor has completing servicing an interrupt request. The first processor includes an interrupt retry means, which includes a refused interrupt register means responsive to a not acknowledge response from the second processor in response to an interrupt requested from the first processor for storing the channel number of the second processor, and level monitor logic connected from the system bus.