Fail safe, fault tolerant circuit for manufacturing test logic on

Abstract

An application specific integrated circuit (ASIC) includes ASIC logic and test logic that includes a fail-safe circuit and test logic circuitry. The test logic in conjunction with input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins. The test logic generates several control signals that can affect operation of the ASIC logic. If any one of these signals is driven active by either a failure or a defect, the ASIC logic would be rendered inoperative. Consequently, each of these control signals is routed to the fail-safe circuit. These control signals include, for example, tri-state and reset signals and other control signals generated by test logic circuitry for the built-in testing of the ASIC. The fail-safe circuit generates a fail-safe control output signal for a corresponding control input signal from the test logic circuitry only during manufacturing testing when a fail-safe enable signal is applied to the fail-safe circuit. Preferably, the fail-safe enable signal is provided on one of the plurality of pins connected to the test logic so that the fail-safe enable signal cannot be generated by a failure or defect in the test logic circuitry.