The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 1995
Filed:
Sep. 16, 1993
Taira Iwase, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method of manufacturing a double-layer gate programmable ROM is disclosed including the steps of: forming a plurality of first gate layers at predetermined intervals on a semiconductor substrate, source and drain regions being formed on the surface of the semiconductor substrate and under the first gate layers, respectively; forming a plurality of second gate layers between the first gate layers, channel regions being formed on the surface of the semiconductor substrate and under the second gate layers, respectively; and selectively implanting ions into the channel regions to program data. In particular, the second gates are formed between the first gate layers so as to provide partial vertically overlapped portions at which one end of each of the second gate layers is overlapped partially with the other end of each of the first gate layers, respectively, and the ion implantation into the channel regions is effected under such a condition that ions can penetrate the first and second layers, but cannot penetrate the overlapped portions of both the first and second layers. Transistors are first formed having a first E-type threshold voltage. Selective ion implantation lowers the threshold voltage of certain of the transistors to program the data into the ROM.