The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 1995

Filed:

Nov. 15, 1993
Applicant:
Inventors:

Richard A Schiebel, Dallas, TX (US);

Michael A Kinch, Dallas, TX (US);

Roland J Koestner, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437106 ; 437185 ; 437911 ; 437965 ; 148D / ; 148D / ;
Abstract

Group II-VI thin film transistors, a method of making same and a monolithic device containing a detector array as well as transistors coupled thereto wherein, according to a first embodiment, there is provided a group II-VI insulating substrate, a doped layer of a group II-VI semiconductor material disposed over the substrate, an insulating gate region disposed over the doped layer, a pair of spaced contacts on the doped layer providing source and drain contacts, a gate contact disposed over the insulating gate region, an insulating layer disposed over exposed regions of the substrate, doped layer, insulating gate region and contacts and metallization disposed on the insulating layer and extending through the insulating layer to the contacts. The thickness of the doped layer is less than the maximum depletion region thickness thereof. In accordance with a second embodiment, there is provided a group II-VI insulating substrate, a first conductive doped group II-VI semiconductor layer disposed over the substrate, a second doped group II-VI layer disposed over the first layer and forming a Schottky barrier therewith, an insulating layer disposed over exposed regions of the substrate, first doped layer and second doped layer and metallization disposed on the insulating layer and extending through the insulating layer to spaced regions on the first layer to form source and drain contacts thereto and to the second layer to form a gate contact thereto. The thickness of said first layer is less than the maximum depth of the depletion region formed by the junction of the first and second layers.


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