The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 1995
Filed:
Dec. 01, 1993
Douglas L Hiser, Berkeley, CA (US);
Kou-Hung L Loh, Pleasanton, CA (US);
IMP, Inc., San Jose, CA (US);
Abstract
A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 volts less than that of the current sink/source FET to ensure that the current sink/source FET operates in its saturated region. A CMOS structure implementing the self-cascoding transconductance circuit has two doped threshold adjust regions formed beneath a gate electrode such that the two doped threshold adjust regions respectively effectuate the cascode and current sink/source FETs which then share the gate electrode. A method of forming the CMOS structure includes forming two self-cascoding transconductance circuits electrically connected in parallel such that they share a common drain region between their respective gate electrodes, and each has one source region. By forming the two self-cascoding transconductance circuits in such a fashion, the effect of alignment errors contributed by each of the parallel connected self-cascoding transconductance circuits is cancelled out for the combined circuit.