The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 1995
Filed:
Feb. 22, 1994
Bruce A Myers, Kokomo, IN (US);
Petrina L Schnabel, Kokomo, IN (US);
Delco Electronics Corporation, Kokomo, IN (US);
Abstract
A method is provided for flip-chip bonding a flip chip to a substrate, which may be a ceramic substrate, printed wiring board, flexible circuit, or a silicon substrate, in which a number of input/output solder bumps are reflowed to both bond the flip chip to the circuit board as well as provide the necessary electrical connection between the flip chip and the circuit board's circuitry. The method enables the height of the input/output solder bumps to be closely controlled thereby providing sufficient spacing between the chip and its substrate, thus optimizing the cleanability and stress relief of the package. Generally, the preferred method involves the use of non-input/output, or 'dummy' solder bumps which are present in sufficient numbers to overcome the tendency for the input/output solder bumps to draw the flip chip excessively close to the circuit board. Because the dummy solder bumps are electrically inactive, their height can be governed by electrically isolated pads on the surface of the circuit board. Consequently, definition of the input/output solder bumps and the dummy solder bumps does not require the use of solder stops or masks during formation or reflow of the solder bumps.