Dynamic complementary pass-transistor logic circuit

Abstract

A dynamic logic circuit style, which may be employed in fast logic circuits, is disclosed. The logic functionality is obtained using complementary pass transistor logic networks. Intermediate nodes and the complementary outputs are precharged to a high level during the precharge clock phase. During the evaluation clock phase, the inputs connected to gates of the pass transistors are constrained to either make a low-to-high transition or to maintain their initial low level; such signals are referred to as rising signals. The inputs connected to current electrodes of the pass transistors are constrained to either make a high-to-low transition or maintain their initial high level; such signals are referred to as falling signals. All signals are organized in pairs of true and complementary signals. In a falling signal pair, only one of the signals is allowed to make a high-to-low transition during an evaluation phase, while the other signal remains at the initial high level. In a rising signal pair, only one of the signals is allowed to make a low-to-high transition during an evaluation phase, while the other signal remains at the initial low level. This ensures that one of the true and complementary output nodes of the pass transistor networks makes a high-to-low transition, while the other node remains at a high level. The high-to-low transition is locally buffered by a clocked regenerative feedback circuit present on both output nodes. The signals on the output nodes form a pair of true and complementary signals which may be used as falling input signals for another circuit stage in the same circuit style. In the regenerative feedback circuits, the inverted output signals are produced and these signals form a pair of true and complementary rising signals which may be used as rising input signals for another circuit stage in the same circuit style.