The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 1995
Filed:
Dec. 27, 1993
Ronald Dekker, Eindhoven, NL;
Henricus G Maas, Eindhoven, NL;
Dirk J Gravesteijn, Eindhoven, NL;
Martinus P Versleijen, Eindhoven, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
A semiconductor device with a semiconductor body (1) is provided with a first and a second bipolar transistor (T1, T2, respectively) in a cascode configuration, in which the semiconductor body (1) comprises, in that order, a collector region (10) and a base region (11) of the first transistor (T1), a region (12) which forms both an emitter region of the first transistor (T1) and a collector region of the second transistor (T2), a space charge region (13), and a base region (14) and emitter region (15) of the second transistor (T2), while the regions form pn junctions with one another which extend parallel to a main surface (2) of the semiconductor body (1). The base region (14) and the emitter region (15) of the second transistor (T2) adjoin a main surface (3) of the semiconductor body (1). According to the invention, a depression (4) is provided in this main surface (3), cutting through the emitter region (12) of the first transistor (T1) which at the same time is the collector region (12) of the second transistor (T2), the space charge region (13), and the base region (14) of the second transistor (T2) and laterally bounding these; regions, while a connection electrode (B1) for the base region (11) of the first transistor (T1) is provided in the depression (4). No latch-up by a parasitic transistor then takes place in the device.