Autonomous pulse train timing controls for time-mark alignment

Abstract

A phase lock loop (700) maintains a freewheeling capability while making phase corrections to a sample clock signal based on a precision timing signal. The phase corrections are dispersed over time such that data reception in uninterrupted so that data integrity is maintained during the phase corrections. The phase lock loop (700) includes a first divider circuit (721) having a divisor n, coupled for dividing the incoming clock signal by n to produce a bit clock signal. A second divider circuit (725) is coupled to the bit clock signal for dividing the bit clock signal to produce the sample clock signal. A phase comparator (717) is coupled to a 1PPS signal that provides a time-mark to said phase lock loop (700) for calibration, wherein the phase comparator (717) measures a number of input clock signal cycles from a predetermined edge of the 1PPS signal to a predetermined edge of the sample clock signal and provides a correction signal indicative of a number of input clock signal cycles and a phase direction error between the sample clock signal and the 1PPS signal for modifying a value of the divisor n for correcting the measured phase error simultaneously with data reception.