The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 1995
Filed:
Oct. 21, 1993
Bernard D Miller, San Jose, CA (US);
Micrel, Incorporated, San Jose, CA (US);
Abstract
A process is described for providing a self-aligned MOS transistor having a selectable gate-drain capacitance. In a self-aligned process for forming a PMOS transistor, a polysilicon layer is etched to expose portions of an n-type substrate in which it is desired to form p+ drain regions. A deep p.sup.+ drain region is then formed in the surface of the substrate so as to have a large diffusion under the polysilicon layer. This large diffusion results in a high gate-drain capacitance. The polysilicon layer is further etched to form a gate. A self-aligned source is then formed using a separate, relatively shallow p+ diffusion. The selectable gate-drain capacitance obviates the need to form separate capacitors on the substrate to use as gate-drain capacitors.