The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 1995
Filed:
May. 28, 1993
Nader Amini, Boca Raton, FL (US);
Patrick M Bland, Delray Beach, FL (US);
Bechara F Boury, Boca Raton, FL (US);
Richard G Hofmann, Boynton Beach, FL (US);
Terence J Lohman, Boca Raton, FL (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.