Random access memory including or gate sensing networks

Abstract

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a and additional pull-up circuits to enhance high speed pair of symmetrical transfer function output inverters operation. The outputs of all of the differential latching inverters may be directly connected to a pair of OR gates with the output of one OR gate signifying that a logical ONE has been read and the output of the second OR gate signifying that a logical ZERO has been read. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.