The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 1995

Filed:

Oct. 06, 1993
Applicant:
Inventors:

Susumu Akamatsu, Osaka, JP;

Atsuhiro Kajiya, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257336 ; 257344 ; 257357 ; 257373 ; 257376 ; 257408 ; 257544 ; 257547 ; 437 34 ; 437 45 ; 437 56 ; 437 74 ; 437913 ;
Abstract

In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.


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