The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 1995

Filed:

Mar. 08, 1993
Applicant:
Inventors:

Tsuyoshi Fujita, Yokohama, JP;

Shoichi Iwanaga, Yokohama, JP;

Hirayoshi Tanei, Yokohama, JP;

Assignee:

Hitachi, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
174261 ; 361795 ; 361767 ; 174255 ;
Abstract

A ceramic thin film hybrid circuit board is provided by flattening the surface of a ceramic multi-layer interconnection substrate, forming capture pads on the flattened surface, filling spaces between the capture pads with an insulating layer composed of a glass material or an organic resin material, grinding the resultant surface until the capture pads are exposed to flatness, and laminating a plurality of thin film interconnection layers on the flattened surface. The ceramic thin film hybrid circuit board has an increased package density of mounted electronic parts such as LSIs and the like because failures of thin film interconnection layer generated owing to the roughness of the surface of the ceramic substrate, defects such as voids and the hollows produced with the capture pads are greatly reduced, and is very suitable for large scale electronic computers, in which the wiring length is reduced so as to reduce the signal delay.


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