Process for fabricating a semiconductor integrated circuit

Abstract

A LOCOS film is formed on the surface of an epitaxial layer. A gate electrode is formed on the epitaxial layer. At the same time that the gate electrode is formed, a lower electrode is formed on the LOCOS film. A diffusion region is formed on each element and then covered with a BPSG film. A contact hole and capacitor exposure are formed in a capacitor element simultaneously. A film of SiN is deposited in layers over the capacitor exposure. The film of SiN covers undesired areas about the capacitor exposure. Excess SiN film outside the desired area over the capacitor exposure is removed by masking and etching to leave the remaining film area over the capacitor exposure to serve as a capacitor dielectric film. Finally, an Al upper electrode is formed over the SiN film to serve as electrode wiring. The process reduces the series resistance of the capacitor element, thereby reducing power required for charging the dielectric, and speeding the charging process. The low resistance eliminates parasitic leakage currents and the formation of parasitic capacitances.