The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 1995

Filed:

Oct. 12, 1993
Applicant:
Inventor:

Hyun S Hwang, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 44 ; 437 40 ; 437 45 ;
Abstract

A process for the fabrication of an MOS transistor. The process comprises the steps of forming a gate oxide film on a substrate, forming a p.sup.+ polysilicon film doped with p type impurity ions over said gate oxide film, coating an insulating film and a photoresist film over said p.sup.+ polysilicon film, in sequence, subjecting the resultant structure to a patterning to expose a portion of said insulating film, applying an etching method to said exposed insulating film with said photoresist film used as a mask, implanting fluorine ions in said p.sup.+ polysilicon film with resultant insulating film used as a mask, removing the remaining photoresist film, carrying out an annealing method to form a low density p.sup.- source/drain regions, applying an etching method to said p.sup.+ polysilicon film to form a gate with said resultant insulating film used as a mask, removing said resultant insulating film, depositing an oxide film entirely over the resultant structure, applying an anisotropic etching to said oxide film to form spacers at side walls of said gate, implanting p type impurity ions in said substrate at a high density to form high density p.sup.+ source/drain regions neighboring said low density p.sup.- source/drain regions, thereby the device having a storage capacity of not less than 256M can be fabricated more reliably and more advantageously.


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