Method of manufacturing an integrated circuit having a memory element

Abstract

If the process were to be changed for optimizing the injection of hot electrons into the channel of the memory transistor in the manufacture of an integrated circuit having an embedded EPROM, this could lead to degradation of the transistors in the logic, in particular in the case of channel lengths below 1 .mu.m. To prevent this, a process is presented by which the non-volatile memory is optimized without the properties of the logic being affected. For this purpose, a first series of steps is performed in which first the floating gate is defined, followed by the source/drain implantation and a side-wall oxidation for obtaining an oxide spacer on the sides of the floating gate. During these steps, the region of the logic to be formed is uniformly protected against implantation and oxidation by the same poly layer from which the floating gate is made. Then, in a second series of steps, the usual CMOS process is carried out whereby first the gates of the transistors are formed, followed by the necessary source/drain implantations.