Semiconductor memory and its layout design

Abstract

Each of two bit lines in a pairing relationship and a word line transition detection signal line bear the same adjunctive capacitance, since connection points provided on plural memory cells establishing connections to each of the bit lines and connection points provided on plural word line transition detection circuits establishing connections to the word line transition detection signal line are laid out into the same form. Each of the memory cells contains a data storage, a first N-channel MOS transistor, and a second N-channel MOS transistor, the data storage being connected to the bit lines through the first and second N-channel MOS transistors. Each of the word line transition detection circuits includes a third N-channel MOS transistor and a fourth N-channel transistor, these transistors being sandwiched between the word line transition detection signal line and the ground. This word line transition detection circuit detects a word line voltage transition, thereby delivering an enable signal to a sense amplifier. The sense amplifier amplifies an electric potential difference between the bit lines on receipt of the enable signal. The third transistor has the same dimensions as the first and second transistors. The gate width of the fourth transistor is set greater than the gate width of MOS transistors forming the data storage.