Apparatus and method for synthesis of signals with programmable periods

Abstract

A synthesized jitter generator employing a novel digital architecture is provided. The apparatus provides period synthesis and controlled sinusoidal and non-sinusoidal jitter modulation functions of a square wave provided at its output. The architecture consists of a coupling of an N+M bit digital accumulator and an N bit synchronous counter to an N bit magnitude compare circuit. The output of the magnitude compare strobes the accumulator when the two inputs are equal in magnitude causing the accumulator to increment synchronously. The output of the magnitude compare is also a digital waveform whose average period is precisely defined by the input word to the accumulator. The lower M bits of the accumulator, which are not connected to the magnitude compare and which represent fractional clock periods, are connected to a programmable delay line which provides a correction in time to the magnitude compare output so that both the instantaneous and the average periods of the digital waveform at the delay line output reflect the accumulator input word. The input to the accumulator may be varied, creating a period modulated output from the apparatus. The modulation of the digital output of the accumulator by way of an adder placed between the accumulator and the magnitude compare allows direct time (jitter) modulation of the output waveform.