Apparatus and method to improve programming speed of field programmable

Abstract

Apparatus and method for compressing configuration bitstreams used to program Field Programmable Gate Arrays (FPGAs) and for decreasing the amount of time necessary to configure FPGAs. In a first embodiment of the present invention, a shift register is employed that enables data bits to be shifted multiple positions per clock cycle through the shift register. As a result, the amount of time required to shift the data bits through the shift register can be reduced by 1/N, where N is the number of positions per clock cycle. The shift register also permits the option of shifting bits through the shift register one bit per clock cycle. In a second embodiment of the present invention, control and address bits are employed to more efficiently manage and reduce the size of the configuration bitstream. Accordingly, one embodiment provides the option of loading data into the array of the FPGA by address column in a non-sequential fashion. In other words, to streamline loading of data into the array from the data shift register, the present invention permits non-sequential writing of frames into the array by column address. Another preferred embodiment of the present invention, permits a previous frame of data (repetitive data) to be loaded into the array without having to resupply the data shift register with the repetitive data. Simple logic control bits indicate how frames of data are to be managed.