Programmable logic device

Abstract

A programmable logic device includes groups of AND logic function gates, the AND logic function gates in each group coupled to a logic OR function output gate associated with that AND logic function gate group. Each AND logic function gate group includes an output AND logic function gate having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that output AND logic function gate. The PLFGs in any set of PLFGs receive the same sets of first logic input groups, and second programmable inputs. Operation of Boolean function generator output stages to carry out logic operations is controlled by first inputs from the logic OR function gates, and second programmable inputs received from logic cells according to logic inputs to said programmable cells. Inputs from the logic OR function gates are selected by programmable OR logic function generators. The PLFGs and BLFGs comprisise logic circuitry to generate output signals determined by any logic function of a plurality of the first logic inputs, and the second inputs. Using this PLD structure, outputs from the PLD can be used to control logic operations performed by the BLFGs using logic values and instructions originating externally of the PLD.