Universal pipeline latch for mousetrap logic circuits

Abstract

Vector logic is implemented by pipelining logic stages comprised of dynamic mousetrap logic gates. A novel pipeline latch is associated with each logic stage of the pipeline. Each pipeline latch has a latch reset mechanism, an input trigger mechanism, a disabling mechanism, a flip-flop mechanism, an output gating mechanism, and a latch enable pull-up mechanism. Moreover, the logic stages are alternately clocked. While the even numbered stages are receiving a high clock signal for instigating propagation, the odd numbered stages are receiving a low clock signal for instigating precharging, and vice versa. The high and low clock times for each stage is substantially equivalent. Due to inherent manufacturing inequalities, clock asymmetry results. An advantaged and disadvantaged phase arises. Because of the novel latch and associated method, pipeline stages operating in the disadvantaged phase can steal time from those operating in the advantaged phase. Further, no minimum clock frequency is required.