The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 1995

Filed:

Sep. 18, 1992
Applicant:
Inventors:

Brian Petersen, Los Altos, CA (US);

Lai-Chin Lo, Campbell, CA (US);

David R Brown, San Jose, CA (US);

Assignee:

3COM Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395325 ; 395250 ; 395425 ; 364D / ; 3642386 ; 3642391 ; 3642393 ; 364240 ; 3642402 ; 3642463 ; 364260 ;
Abstract

A data path aligner transfers data from an input having N byte lanes with byte enable bits to an output having N byte lanes. The aligner includes first stage having N-1 selector/registers, and a second stage having N selector/registers. Each of the N-1 selector/registers S1(i) in the first stage has inputs including input lanes L(j) for j going from i+1 to N. Each of the selector/registers S2(i) in the second stage has inputs including input lanes L(k) for k going from i to 0, and for selector/registers S2(i) for i less than or equal to N-2, the inputs include the output of a first stage selector/register S1(i). The outputs of the second stage selector/registers supply data selected from the respective inputs to output segment lanes. All of these selector/registers are controlled by a common select signal derived from a data path offset, and all selector/registers are clocked by a common clock.


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