Semiconductor memory device

Abstract

A semiconductor memory device includes a data line for receiving a voltage and an inverted data line having a voltage inverted relative to the voltage received by the data line; a first transistor and a second transistor for selecting a memory element for writing in data and reading out data through the data line and the inverted data line, respectively; two inverters, each inverter including a first p channel transistor and a first n channel transistor with the input and the output of the one inverter respectively connected to the output and the input of the other inverter and between either the source and the drain of the first transistor or the drain and the source of the second transistor; and a second p channel transistor connected in series to the first p channel transistor of one of the two inverters. When the same data, '0' or '1', is to be written into all memory elements, the second p channel transistor is turned off to inhibit 'H' driving of the inverters and no 'H' driven output of the inverter collides with the output of an 'L' driven writing driver. As a result, writing of the same data into all memory elements can be performed without malfunction.