The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 1995
Filed:
Jun. 12, 1991
Wilm E Donath, Pleasantville, NY (US);
Wing K Luk, Yorktown Heights, NY (US);
Donald T Tang, Mt. Kisco, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus for minimizing the total power of a logic network subject to timing constraints. The method describes a procedure to assign power and/or delay to each circuit in a logic network such that the total power is minimized and the arrival time requirement at the outputs of the logic network is met. A subset of circuits in the logic network are powered up and powered down in repeated succession in order to minimize the total power of the logic network.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile