The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 1995

Filed:

Jun. 25, 1993
Applicant:
Inventors:

Hideki Ohtaka, Neyagawa, JP;

Tatsuro Juri, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358336 ; 360 381 ; 360 53 ;
Abstract

A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing digital signal presented in sync blocks is disclosed. Each sync block has a fixed area for low frequency data and five subsequent sync blocks define a sharing group for sharing high frequency data. The signal processing apparatus includes an inner and outer correction circuit for correcting errors in the sync blocks. An error flag is provided to a sync block which still has an error remaining after the processing in the correction circuit. A memory is provided for storing errorless sync blocks of one frame. A substitution switch is provided for passing the errorless sync blocks, but substituting a sync block stored in the memory for a sync block still having some errors. Five sync blocks produced from the substitution switch are held in a delay. When no substitute sync block is detected in the five sync blocks in the delay, the data in the five sync blocks are decoded by a bit rate reduction decoder. But, when one to four substitute sync block is detected in the five sync blocks in the delay, only the low frequency data of the five sync blocks in the fixed area are decoded by the bit rate reduction decoder.


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