Wet/dry anti-fuse via etch

Abstract

An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area. The second recessed area extends from the bottom of the first recessed area completely through the remaining oxide layer to the underlying metallic layer. In so doing, when amorphous silicon is deposited into the vias, cusping of the amorphous silicon within the vias is substantially reduced. As a result, the step of depositing a spacer oxide to fill in notches created by cusping of the amorphous silicon layer is eliminated. Consequently, when the amorphous silicon is removed or etched from selected strap vias, because no spacer oxide has been deposited, no deleterious residue or 'dog ears' of amorphous silicon remain within the strap vias.