The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 1995

Filed:

Jan. 29, 1993
Applicant:
Inventors:

Craig Heikes, Ft. Collins, CO (US);

Robert H Miller, Jr, Loveland, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364745 ; 364748 ;
Abstract

A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.


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