The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 1995
Filed:
Feb. 03, 1993
Jeffry D Yetter, Ft. Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A dynamic mousetrap logic gate implements a self-timed monotonic logic progression via a novel vector logic method. In the vector logic method, a vector logic variable is defined by a plurality of vector components situated on respective logic paths. Boolean as well as non-Boolean variables can be represented. Further, timing information is encoded in the vector logic variable itself by defining the vector logic variable as invalid when all the vector components currently exhibit a logic low and by defining the vector logic variable as valid when a subset of the vector components exhibits a logic high. With a plurality of valid vector logic states, subsets defining valid vector logic states are nonoverlapping. The mousetrap logic gate comprises a plurality of gate components in parallel, corresponding with each output vector component. Each gate component has an arming mechanism, a ladder logic, and an inverting buffer mechanism. The ladder logic performs logic functions on one or more input vectors and provides the result to the inverting buffer mechanism. The arming mechanism periodically precharges the inverting buffer input to drive the gate component output to a logic low until the inverting buffer mechanism is triggered by the ladder logic.