The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 1995

Filed:

Jul. 13, 1992
Applicant:
Inventor:

Satoru Sonobe, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02B / ;
U.S. Cl.
CPC ...
307125 ; 327115 ; 327141 ;
Abstract

This variable clock dividing circuit is provided with a plurality of dividers coupled in succession. A first of the dividers divides the basic clock by a predetermined dividing ratio and provides an output clock signal to the next divider in succession, while the last divider receives an output clock signal from the next to last divider. The dividing circuit selectively outputs one of the output block signals from the dividers using a switching circuit. A phase synchronization circuit synchronizes the phase of the clock input to the plurality of dividers based on the basic clock. The phase synchronization circuit further comprises a buffer to delay the basic clock before inputting it to the first divider, and a plurality of AND gates. Each of the AND gates corresponds corresponds to the second to last dividers and receives the basic clock and the outputs from all the preceding dividers.


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