Efficient channel and control unit for host computer

Abstract

An I/O system including a processor, a multitasking operating system and DMA hardware efficiently controls a transfer of data between a main memory and memories of different types of devices by minimizing context switches between tasks and wait times of the tasks. A plurality of validation routines are used to validate a plurality of commands when the validation routines are called. Each of the commands corresponds to a specific type of I/O operation and a specific one of the device memories to participate in the I/O operation with the main memory. Each of the validation routines is device type specific and command type specific. A general routine responds to each of the commands by identifying and calling the validation routine which corresponds to the type of I/O operation and type of device which are specified in the command. The general routine initiates I/O hardware after the validation routine validates the command. After the I/O hardware completes the I/O operation, it signals a command completion routine which is command specific and device type specific. In response, the command completion routine signals to the general routine a state of the I/O operation. Each of the validation routines executes on the same task as the general routine to minimize context switches, and each of the command completion routines executes on a different task than the general routine to minimize wait time for the command completion routine.