The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 1995
Filed:
Dec. 13, 1991
Gary E Benzschawel, Chippewa Falls, WI (US);
Lonnie R Heidtke, Chippewa Falls, WI (US);
Steven S Chen, Chippewa Falls, WI (US);
Fredrich J Simmons, Eau Claire, WI (US);
George A Spix, Eau Claire, WI (US);
Cray Research, Inc., Eagan, MN (US);
Abstract
Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory. Direct memory access requests are queued at the channel while higher-priority serial transfer requests are serviced. Direct memory access is provide in 64-word blocks designated by perimeter packets indicating a number of blocks, starting address in main memory, starting address in solid state memory, and an indication of the direction of transfer.