The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 1995

Filed:

Feb. 26, 1992
Applicant:
Inventors:

John W Blackledge, Jr, Boca Raton, FL (US);

Grant L Clarke, Jr, Boca Raton, FL (US);

Richard A Dayan, Boca Raton, FL (US);

Kimthanh D Le, Boynton Beach, FL (US);

Patrick E McCourt, Delray Beach, FL (US);

Matthew T Mittelstedt, Delray Beach, FL (US);

Dennis L Moeller, Boca Raton, FL (US);

Palmer E Newman, Boca Raton, FL (US);

David L Randall, Pompano Beach, FL (US);

JoAnna B Yoder, Delray Beach, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
380-4 ; 380-3 ; 380 52 ;
Abstract

This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, at least one erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for invalidating any privileged access password stored in the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.


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