On chip current limiter

Abstract

A current limiting circuit and technique is provided for preventing excessive current supplied to a circuit and for providing self-recovery characteristics thereto. The current limiting circuit includes an input for receiving a supply voltage for supplying power to the monitored circuit and an output for providing the power to the desired circuit being monitored. The circuit employs a drive transistor having a source connected to the input and a drain connected to the output. The drive transistor further includes a gate for receiving a control signal. A current mirror circuit is provided for sensing a current overload and adjusting the control signal to indicate the amount of current drawn. During normal current draw, the circuit provides the supply voltage as the output. When excessive current draw is detected, the drive transistor is turned off and the output current is thereby cut off. When the current decreases to normal current loads, the drive transistor is turned back on. In addition, a reset signal may be further generated when excessive current is detected to reset the internal logic on a chip, so as to correct the problem causing the excessive current draw. Furthermore, the monitored circuit and herein described current limiting circuit may be fabricated together on the same die or chip.