The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 1995
Filed:
Sep. 23, 1993
Peter H Voss, Watsonville, CA (US);
Shahryar Aryani, Santa Clara, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A buffer utilizing the pseudo-ground hysteresis of the present invention contains first and second stage switching elements and a resistive element. The pseudo-ground hysteresis is implemented via a ground path from the switching elements. The first stage switching element is configured to have a first DC voltage trip point, and the second stage switching element is configured to have a second DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, a first current (I.sub.1), from the first stage switching element, and a second current (I.sub.2), from the second stage switching element, is generated. When the input voltage equals the first stage DC voltage trip point, the first and second stage switching elements transition. During the transition of the input voltage from the second state to the first state, the total current flowing through resistive element is reduced, and the voltage at the resistive element decreases. Consequently, the first stage switching element transitions at a voltage level offset from the first DC voltage trip point to provide hysteresis for the second state to first state transition of the input voltage.