Frequency divider circuit

Abstract

A programmable divide-by-N or divide-by-N+1/2 circuit is responsive to an input clock signal and to a plurality of binary-coded data signals corresponding to the divisor for providing an output clock signal having a frequency which is the frequency of the input clock signal divided by the value encoded on the data signals. The circuit includes two separate down counters 10, 12--one decrementing on the positive-going edge of the input clock signal and the other decrementing on the negative-going edge of the input clock signal. If the divisor is an integer N, the negative-clocked circuitry 12 is disabled and the positive-clocked circuit 10 counts down from N to 1 continuously. If the divisor is N+1/2, both counter circuits are used. In this case, both counters are preset with the value N, the positive-edge-triggered counter 10 decrements from N to zero while the negative-edge-triggered counter 12 decrements from N to one. Then, both are preset with the value N, and this time the positive-edge-triggered counter 10 decrements to one while the negative-edge-triggered counter 12 decrements to zero. This count swapping occurs continuously. The resulting output signals are combined in a shaping circuit 14 to produce a frequency-divided output signal having a preselected low-state pulse width.