The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 1995
Filed:
Feb. 01, 1994
Shuuichi Miyaoka, Ohme, JP;
Kazuhisa Miyamoto, Ohme, JP;
Masanori Odaka, Kodaira, JP;
Hideo Sawamoto, Hadano, JP;
Michiaki Nakayama, Ohme, JP;
Mitsugu Kusunoki, Ohme, JP;
Masato Ikeda, Ohme, JP;
Takashi Ogata, Ohme, JP;
Kouji Kobayashi, Ohme, JP;
Masao Kato, Hadano, JP;
Tsutomu Sumimoto, Hadano, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Microcomputer System, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.