The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 1995
Filed:
Sep. 30, 1992
Applicant:
Inventor:
Johann Massoner, Villach, AT;
Assignee:
Siemens Aktiengesellschaft, Munich, DE;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H / ;
U.S. Cl.
CPC ...
327206 ; 327399 ;
Abstract
An analog delay circuit configuration includes a switching stage. A capacitor is connected upstream of the switching stage. A controlled current source has a current being definitive for a charging state of the capacitor. The current source is clocked with a pulse-to-interval ratio of less than 1. A current mirror configuration reduces the current of the current source. An inverter stage is coupled to the current mirror configuration and has an output side connected to the capacitor.
Massoner, Johann. (1995). Analog delay circuit configuration (U.S. Patent No. 5382840). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5382840
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile