Detection of skew fault in a multiple clock system

Abstract

A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock terminals of both of these flip-flops are connected to one of the clock phases, and one of the clock phases is coupled to a delay circuit on the D input terminal of one of the flip-flops. The delay circuit is adjustable to correspond to the clock pulse delay that is inherent in the circuit that is being monitored to control the maximum amount of clock skew that is allowable before this flip-flop will set. If the clock skew exceeds this allowable time, a skew fault occurs and the flip-flop will set. The circuit compares the initiation of one clock phase against the initiation of the other clock phase and to determine when the initiation of one clock phase occurs earlier than the initiation of the other clock pulse by a time duration that exceeds a predetermined allowable skew amount of time. Majority voting circuits may be employed to allow for detection failure of more than one skew fault detection circuit.