The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 1995

Filed:

May. 28, 1993
Applicant:
Inventors:

Janet E Wedgwood, Bethpage, NY (US);

John F Petrsoric, New Hyde Park, NY (US);

Assignee:

Grumman Corporation, Bethpage, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
36472416 ; 36472419 ;
Abstract

A complex adaptive Finite-Impulse-Response filter for processing complex digital data having real and imaginary data portions that includes a first data path for receiving and processing the real data portion of the complex input and a second data path for receiving and processing the imaginary data portion. Each first and second data path includes a corresponding plurality of adaptive weight circuits and accumulator circuits to perform respectively, multiplications of input data with a set of updatable coefficient data and accumulations of the multiplication results obtained. Two of multiplication results are obtained for each data path and a subset from each are accumulated to form a real output portion and imaginary output potion for the filter. A time delay circuit is provided to allow for proper time multiplexing of the imaginary output portion. The plurality of adaptive weight circuits have associated therewith first and secondary memory storage banks for storing the current coefficient data values. Alternate first and second memory storage banks are provided to receive updated coefficient data for use by the adaptive weight circuits at the request of the host processor. While the coefficient data stored in the first and second memory storage circuits are being used by the adaptive weight circuits for processing thereof, the coefficient data values may be updated in the first alternate and second alternate memory storage banks and vice versa.


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