The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 1995
Filed:
Sep. 08, 1993
Andreas Grundl, Munich, DE;
Bernhard Hoffmann, Starnberg, DE;
Grundl & Hoffmann, , DE;
Abstract
A half-bridge arrangement for switching electrical powers, wherein at least two semiconductor switches (14, 21; 15, 20; 16, 19; 17, 18) forming a half-bridge (12a; 12b; 12c; 12d) are connected in series; each semiconductor switch (14, 21; 15, 20; 16, 19; 17, 18) is provided with a control input (G) which is connected to a driving circuit (23, 24); each first semiconductor switch (14; 15; 16; 17) is at a high voltage potential (V.sub.ss) with its source terminal (S); each second semiconductor switch (18; 19; 20; 21) is at a low voltage potential (V.sub.DD) with its drain terminal (D); the drain terminal (D) of each first semiconductor switch (14; 5; 16; 17) is connected with the source terminal (S) of each respective second semiconductor switch (18; 19; 20; 21) for providing an output terminal (A); and at least one capacitor assembly (30) is arranged between the high and the low voltage potential (V.sub.SS, V.sub.DD); is characterized in that said driving circuit (23, 24) activates said semiconductor switches (14, 21; 15, 20; 16, 19; 17, 18) by a control signal with a switching frequency of more than 20 kHz; said capacitor assembly (30) is made up by at least one sheet capacitor (30a) at a printed circuit board (33) carrying semiconductor switches (14, 21; 15, 20; 16, 19; 17, 18) and by at least one wrap capacitor (30b) designed as a hollow coil (40); said semiconductor switches (14, 21; 15, 20; 16, 19; 17, 18) being arranged within said wrap capacitor (30b); and a fluid cooling being provided within the hollow coil (40).