Overvoltage tolerant output buffer circuit

Abstract

A tristate output buffer circuit provides overvoltage protection from voltage signals on a common bus having a higher voltage level than the internal high potential power rail of the tristate output buffer circuit. A high potential level pseudorail (PV) is coupled to the NWELL of a P channel output pullup transistor (P4). A comparator circuit (P5,P6) couplings the pseudorail (PV) to the output (VOUT). The comparator circuit passgates (P5,P6) are constructed to couple the pseudorail (PV) to the high potential power rail (VCC) for VOUT<VCC and to couple the pseudorail (PV) to the output (VOUT) for VOUT>VCC. A feedback transistor (P1) couples the pseudorail (PV) to an internal node of the tristate output buffer circuit at the control gate node of the output pullup transistor (P4). The feedback transistor (P1) control gate node is coupled to a tristate enable input (EN) for turning on the feedback transistor (P1) during the tristate operating mode and holding off the output pullup transistor (P4). At least one N channel pullup transistor (N1,N2) is coupled between the control gate node of the output pullup transistor (P4) and high potential power rail (VCC) to isolate overvoltage at the internal node from the high potential power rail (VCC). The N channel pullup transistors (N1,N2) are selected to have a turn on voltage threshold VTN less than the absolute value of the turn on voltage threshold VTP of the P channel output pullup transistor.