Fifo memory controller for a digital video communications channel having

Abstract

A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written. Because different thresholds are assoicated with the portions, data, such as a digitized video signal having active line portions separated by control portions for example, can be transferred via the FIFO from one system to another more efficiently in terms of communication bandwidth usage.