The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 1995
Filed:
Aug. 04, 1993
Yoshimi Matsumoto, Kanagawa, JP;
NEC Corporation, Tokyo, JP;
Abstract
A parallel-serial data converter according to the present invention comprises a n-th latch circuit which latches the sign bit at the most significant bit of parallel data, a n-1th selector which selects either of the n-1th bit or the ground level, a n-1th latch circuit which latches the output from the selector n-1, a i-th selector which selects either of the i-th bit (i=n-2, n-3, . . . , 2, 1) of the parallel data or the output from the i+1th latch circuit, a i-th latch circuit which latches the output from the i-th selector, a n-th selector which selects either of the output from the first inverter to reverse the output from the first latch circuit or the output from the first latch circuit, a n+1th selector which selects either of the output from a second inverter to reverse the output from the n-th selector or the output from the n-th selector for output as serial data in two's complement notation, a set latch circuit which is set according to the STORE signal and latches the output from the first AND circuit to take the logical AND the output form the n-th selector and the selection signal as well as a second AND circuit which takes the logical AND the output from the set latch circuit and the output from the n-th latch circuit for output as the selection signal.