The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 1995
Filed:
Jan. 21, 1992
Akihiko Ochiai, Kanagawa, JP;
Sony Corporation, Tokyo, JP;
Abstract
In a sea-of-gate structure gate array in which a plurality of logic gates are arrayed on a semiconductor chip, resistance devices or capacitive devices are formed without reducing the gate scale to form analog components to render the gate array into a hybrid gate array including the analog components. A number of MOS transistors to be formed without vacancies on the chip surface are formed in a thin silicon section on an insulating layer 15. The logic gates arrayed on the chip is of the SOI structure. Below the insulating layer 15, a lower capacitor electrode 12, a dielectric film 13, an upper capacitor electrode 14 and a resistance element are formed so as to be buried in an insulating film 11 on a supporting substrate 10 or in an insulating substrate. The capacitor and the resistance are led to the chip surface by means of a contact hole 23 provided in the insulating layer 15. A grinding stop 16 is formed in the insulating layer 15. The thin silicon section of the SOI structure is produced by grinding the substrate.