The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 1995
Filed:
Sep. 17, 1991
Applicant:
Inventors:
Goro Suzuki, Hitachi, JP;
Masahiro Iwamura, Hitachi, JP;
Tetsuya Yamamoto, Hitachi, JP;
Yoshio Okamura, Akishima, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257208 ; 257211 ; 437 51 ; 364488 ; 326 39 ; 326 41 ; 326101 ;
Abstract
An LSI layout design method is for placing on a chip a plurality of different master cells, each of which has a plurality of signal wiring conductors not connected to internal elements, for example, transistors, resistors and so on for realizing a certain logic function.