Apparatus and methods for reducing numbers of read-modify-write cycles

Abstract

Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.